STA - Static Timing Analysis Lead (8+ Years)

Position Overview We are seeking an experienced STA Lead with strong expertise in Static Timing Analysis for complex ASIC/SoC designs. The ideal candidate will be responsible for driving timing closure activities across block and full-chip level designs while collaborating closely with RTL, Physical Design, DFT, CTS, and Signoff teams. This role requires deep understanding of timing methodologies, advanced process nodes, low-power design considerations, and full-chip timing signoff flows for high-performance semiconductor products. Key Responsibilities Lead STA activities for block-level and full-chip ASIC/SoC designs. Drive timing closure across synthesis, place-and-route, CTS, and signoff stages. Perform: Static Timing Analysis Timing constraint development Timing debugging Timing signoff Analyze and resolve setup, hold, noise, and clock-related timing violations. Work closely with RTL, Physical Design, DFT, and Architecture teams to achieve timing closure targets. Validate timing co...